August 9, 2004 
  FPGA Direction 
 
 
Introduction

As is common knowledge in the EDA industry FPGAs (Field Programming
Gate Arrays) and ASICs (Application Specific Integrated Circuits)
are at opposite poles of the logic market. The table below presents
a qualitative comparison.
 

Table 1 Characteristics

These characteristics make one approach more attractive for certain
kinds of applications and the second approach for other kinds of
applications. High volume, cost sensitive applications would favor
ASICs, while applications with low volumes, time to market pressures
and high cost would favor FPGAs.

Many firms use FPGAs during the early design phase and preproduction
phases and then switch later to ASCI for volume production. For
applications whose future commercial success is unknown the FPGA
route offers lower risk Some firm may use FPGAs to establish a
presence in a new or emerging market thereby gaining first mover
advantage at a time when cost is not the dominant factor in the
customers' mind. With the increasing NRE costs for ASICS and the
shrinking market windows, particularly in the consumer products
sphere, FPGAs are becoming increasingly attractive. According to
Gartner Dataquest the number of FPGA/PLD starts in 2003 was around
80,000 versus almost 3,800 ASIC starts.

Xilinx, the industry leader in FPGAs, estimates the total logic
market at $57 billion composed of ASIC $14.0B, PLD (Programmable
Logic Devices) at $3.3B, ASSP at $31.5B and other general purpose
logic at $8.5 B. The PLD market consists of FPGA at $2.8B and CPLD
at $0.5B. Obviously, Xilinx and its competitors would like to find
ways to expand the market for FPGAs. There are two general
approaches. One approach is to lower the per unit production cost of
FPGA to attack the low end opportunity and the other is to increase
its capability to compete at the high end for high-performance DSP,
high-speed I/O, embedded processing and next generation
applications. Unit production costs can be lowered by leveraging 90
nm technology and 300 mm wafers. Cost can also be lowered by
designing FPGAs with less processing power, less memory, smaller
feature sets and so forth.
  

Table 2 Application Areas for FPGAs


Industry Players


Table 3 Total Revenue of Industry Players
Calendar quarters
  

Figure 1 Market Share

For the last quarter Lattice Semiconductor reported that FPGAs at
$11 million constituted 18% of total revenue while growing 24% year
over year. Altera said that FPGA accounted for 69% of total revenue
while growing 73% year over year.



Xilinx

Xilinx was founded in 1984 and shipped its first commercial product
in 1985. Today Xilinx employs around 2,600 people. Xilinx claims
more than 7,500 customers worldwide and more than 50,000 design
starts. This amounts to more than half the world demand for FPGAs.
Based on calendar 2003 revenues, Xilinx estimates it is now the
third largest ASIC company worldwide.

As a "fabless" supplier, Xilinx partners with leading semiconductor
manufacturers such as IBM Microelectronics, UMC (United
Microelectronics Corporation) and Seiko. Xilinx has collaborated
with UMC as its primary manufacturing partner for high-volume
production of the Xilinx programmable chips. In March 2002, Xilinx
commenced a manufacturing collaboration with IBM that resulted in
the integration of IBM's PowerPC microprocessor with Xilinx FPGA
technology to form a new type of hybrid chip family, the Virtex-II
Pro, for use in communications, storage, and consumer applications.
In June 2002, the companies announced a second technology agreement
under which IBM is licensing FPGA technology from Xilinx for
integration into IBM's Cu-08 ASIC product offering. Xilinx is
producing programmable logic devices on a state-of-the-art 90 nm .13
micron process and utilizing the cost efficiencies of 300mm wafer
manufacturing.

In March 2002, through partnering with IBM, WindRiver Systems, and
Conexant, Xilinx delivered the Virtex-II Pro programmable system
solution. Virtex-II Pro FPGA includes programmable logic fabric with
up to four high-speed embedded PowerPC processors and integrated
3.125 gigabit RocketIO serial transceivers.

In December 2003 Xilinx unveiled its new Application Specific
Modular Block (ASMBL pronounced as "assemble") architecture. At the
heart of the ASMBL architecture is a modular framework of silicon
subsystems, enabling a new FPGA development methodology for rapid
and cost-effective deployment of platforms targeted to different
application domains. The new highly modular ASMBL architecture makes
use of advanced flip-chip packaging technology and eliminates
geometric layout constraints associated with traditional chip design
such as hard dependencies between I/O count and fabric array size.
The ASMBL architecture also addresses the increasingly more
stringent requirements for on-chip power and ground distribution by
allowing power and ground to be placed anywhere on the chip. The
architecture also enables the scaling of hard IP. The Xilinx
designers can vary the number and ratio of different functional
columns to create a platform or family of different sized devices,
each best suited for a certain domain of applications depending on
the desired type of functional attributes. Platforms can be created
with different mixtures of columns based features: logic, memory,
DSP, processing and high-speed I/O. This approach enables the right
feature mix at the lowest cost.

On June 7 Xilinx unveiled details of its fourth generation in the
Virtex product, the Virtex-4 Platform FPGAs. Since its 1998
introduction, the company has shipped over 15 million Virtex devices
and generated nearly $2.5B in cumulative revenue. The Virtex-4
Platform product line based upon ASMBL architecture offers multiple
domain-optimized platforms. The initial Virtex-4 family includes
three platforms; Virtex-4 LX for logic, Virtex-4 SX for very high
performance signal processing, and Virtex-4 FX for embedded
processing and high-speed serial connectivity. Each platform will
offer a range of device options, a total of 14 devices.

The LX Platform FPGAs are optimized for general logic applications
and offer the highest logic density and most cost-effective
high-performance logic and I/Os. The SX Platform FPGAs are optimized
for very high-performance signal processing applications such as
wireless communication, video, multimedia and advanced audio that
may require a higher ratio of XtremeDSP slices to logic. The FX
Platform FPGAs are assembled with capabilities tuned for complex
system applications including high-speed serial connectivity and
embedded processing, especially in networking, storage,
telecommunications and embedded applications. The
embedded-processing domain is dominated by control flow operations
involving complex data types. The connectivity-domain involves
message-based processing and is dominated by asynchronous data flow
operations. Initial engineering samples of the Virtex-4 LX Platform
FPGAs will be available in summer 2004, with SX and FX platforms to
follow. This approach provides system designers with flexibility,
price, performance and time-to-market benefits.

Xilinx changed its definition of ASMBL from Application Specific
Modular Block to Advanced Silicon Modular Block to make it clear
that they intended to pursue its standard products path with
domain-optimized devices, rather than 'Application Specific' devices
such as ASSPs and ASICs.

Common to all the Virtex-4 Platform FPGAs is the traditional highly
flexible "programmable logic" with its programmable interconnect and
I/O structures. Other enhanced features in the Virtex-4 family
included new Digital Clock Management, faster block RAM, enhanced
PowerPC 405 core with an Auxiliary Processor Unit for direct
interface between CPU and fabric, 1Gbps parallel I/O, 0.6 - 11.1
Gbps serial transceivers and an enhanced XtremeDSP slice with built
in MAC functionality.

In April 2003 Xlinix introduced the Spartan-3 solution as the
successor of the Spartan-IIE family of low cost FPGAs. The Spartan-3
family consists of eight devices ranging from 50K to 5M system gates
with up to 1.8 Mbits of Block RAM. The product is architecturally
based on the Virtex-II series products and has features such as
block RAM, clock management, and 18x18 multipliers to support
high-performance DSP applications. However, Virtex-II and Virtex-II
Pro devices will have a higher density range and more features and
more performance across the board than that of the Spartan-3 device
offering. A unique feature is staggered pad technology which has two
rows of I/O on each edge of the chip versus one found in all other
FPGAs. Due to this feature, Spartan-3 devices offer up to 784 I/O
pins, 50% more than in Spartan-IIE devices. Spartan-3 devices up to
400,000 system gates sell for less than $6.50 in volume and devices
with 1 million system gates will sell for under $12.

To compare and measure the device costs, Xilinx defines two metrics.
The first metric is "Cost per Logic Cell" (CPL), and is a direct
measurement of the density of a device. The more aggressive the
process, the more logic per unit area. Spartan-3 offers a 30+% lower
CPL over competing low-cost FPGAs. The other metric is "Cost per IO"
(CPI). Where many custom silicon solutions use linear bond pads,
arranged around the periphery of the device, Spartan-3 employs a
staggered I/O approach, supporting 30% more I/O cells in the same
area.

In mid June Xilinx announced that sales of low cost Spartan Series
FPGAs passed $750 million since the introduction in 1998. More than
80 million devices have shipped to over 13,000 customers since the
family's debut. On July 1 Xilinx announced that reduced power Xilinx
Spartan-3 FPGAs would be available in the fourth quarter of calendar
2004.

The Virtex-II EasyPath devices are standard Virtex-II FPGA circuits
that are verified to meet the requirements of a specific customer
application. Xilinx has created an innovative test methodology that
leverages the re-programmability of FPGAs to isolate and test all
resources required of a specific design, based on data generated by
Xilinx implementation tools. Xilinx then creates a set of
configuration patterns and test vectors that are combined into a
custom test program that validates the functionality of all
resources required by a specific customer design. It also determines
that any defects that may be present in unused parts of the chip
will not affect the performance or reliability of the specific
application. Because the Virtex-II EasyPath device implements the
specific application in the exact same circuit as an FPGA device, a
100 percent match to the performance and functionality is
guaranteed, and no board or system re-verification or
re-qualification is necessary.

EasyPath reduces test time and increases yield, lowering overall
cost that is passed on to the customer, and it provides customers
with a no-risk migration to a lower cost solution. Easy path reduces
cost by 30% to 80% with no engineering resources, no conversion risk
and no performance or functionality change. Production units can be
shipped eight weeks from initial order. Subsequent order for the
same application can be shipped within a few weeks.



Altera Corporation

Altera was founded in 1983. The company developed the first
reprogrammable logic device (PLD), the EP300 in 1984. Altera
expanded its technology leadership in 1988 with the
product-term-based MAX architecture and, in 1992, with the look-up
table (LUT)-based FLEX architecture. Altera pioneered the
system-on-a-programmable-chip (SOPC) era with the recent
introduction of newer, more powerful and efficient architectures,
the Quartus II development system, and an extensive IP offering.

On February 2nd Altera launched newly architected, high-density
Stratix II family of FPGAs. Stratix II devices offer more than
double the logic density and 50 percent higher performance at 40
percent lower cost than first-generation Stratix devices. The
Stratix II family's innovative new architecture is based on a unique
logic structure made up of adaptive logic modules (ALMs). The new
logic structure allows logic to be shared among adjacent logic
functions, delivering efficient logic utilization and high
performance. Each ALM contains two adaptive look-up tables (ALUTs).
With up to eight inputs to the combinational logic block, one ALM
can implement up to two independent functions, each of varying
widths, including any function of up to six inputs and certain
seven-input functions. This optimized utilization significantly
reduces logic resource requirements. Comprised of a unique mix of
combinational, arithmetic, and register logic, an ALM is 2.5 times
more powerful than the original Stratix logic element. ALMs deliver
more logic capacity in a smaller physical area which equates to
lower cost. Stratix II devices have more than twice the logic of
Stratix FPGAs with the equivalent of close to 180,000 logic elements
(LEs). Stratix II FPGAs include all the popular Stratix family
system-level features, such as hard DSP blocks and TriMatrix memory.
In addition, Stratix II devices include new features, such as
advanced encryption standard (AES)-based design security technology,
dynamic phase alignment (DPA) circuitry, and support for new
external memory interfaces.

On June 30 Altera announced that it has begun shipping its new
Stratix II family. Volume prices at the end of 2004 start at $125 in
25,000 unit volumes. Stratix II devices are based on a 1.2-V, 90-nm,
9-layer-metal, all-layer-copper process technology from TSMC and
will use a low-K dielectric and will be manufactured on 300-mm
wafers.

Altera's introduced its first-generation low cost Cyclone FPGAs in
December 2002 as a low-cost alternative for the next generation of
applications currently using low-to-moderate-density ASICs. Altera
has since shipped more than 3 million units to over 3,000 customers.
On June 28th Altera introduced Cyclone II, the second generation of
low cost FPGAs. Cyclone II devices offer 30 percent lower cost and
more than three times the density of the first-generation devices
Cyclone II FPGAs are built on 90-nm process technology, while the
Cyclone family uses 0.13 çm. The second-generation devices also
offer more features such as: embedded multipliers, more PLLS,
support for more I/O standards, and interface to newer memory
devices. The Cyclone II device family includes six members ranging
in density from 4,608 to 68,416 logic elements (LEs) over three
times more than was available with first-generation Cyclone devices.
Cyclone II devices feature up to 150 embedded 18 x 18 multipliers,
which support low-cost DSP applications. Cyclone II devices contain
M4K memory blocks consisting of 4,608 bits per block and offering up
to 1.1 Mbits of on-chip memory supporting multiple configurations
including true dual-port and single-port RAM, ROM, and FIFO buffers.
The Cyclone II device family is based on the 1.2-V, 90-nm, low-k
dielectric process from TSMC, the same process technology used for
Altera's high end Stratix II devices.

Engineering samples of the first member of the Cyclone II device
family, the EP2C35 device, will be available in February 2005, with
the remaining family members rolling out in the next six months.
Volume pricing for the EP2C35 will be $22 in 250,000 unit volumes in
the smallest package and slowest speed grade.

The Cyclone architecture consists of vertically arranged logic
elements (LEs), embedded memory blocks, and phased locked loops that
are surrounded by I/O elements (IOEs). A highly efficient
interconnect and low-skew clock network provide connectivity between
each of these structures for clock and data signals. Area-efficient
IOEs are grouped into I/O banks around the device, offering
significant capabilities while consuming minimal die area.

More than 40 IP cores are optimized for Cyclone II devices. Various
IP cores from Altera and Altera Megafunction Partners Program (AMPP)
partners are specifically optimized for the Cyclone II architecture.

Altera approach to cost reduction is to offer a migration path from
FPGA to Structured ASIC. Altera's HardCopy devices are structured
ASICs that have common base arrays with two or three top layers of
metal for customization. HardCopy devices preserve the architecture
and features of their equivalent high-density FPGAs with the
programmability removed. With a die size that is 60 to 70 percent
smaller than the original FPGA, these low-cost devices provide
performance comparable to standard cell ASICs and consume
significantly less power. HardCopy devices are built on the same
process technology and go through a seamless migration process of
the FPGA design. These were discussed in previous editorial on
Structured ASICS. There are no plans to support a migration path
from Cyclone II devices to HardCopy structured ASICs.



Summary

Xilinx and Altera combine for 86% of the PLD market. They both have
a two pronged attack on expanding their market opportunities. Xilinx
offers its Virtex family at the high end and Spartan at the low end.
Altera offers Stratix at the high end and Cyclone at the low end.
Lower cost FPGS are achieved by leveraging 90 nm processing
technology and 300 mm wafers. The lower cost FPGAs also offer less
processing power, less memory and smaller feature set. The high end
FPGAs have unique architectures. The latest from Xilinx offers
multiple domain-optimized platforms based upon ASMBL architecture.
The latest from Altera is based upon a unique logic structure made
up of adaptive logic modules. The two vendors have introduced second
generation families at both the low and high end during this
calendar year.

The biggest difference between the vendors lies in their approach to
cost reduction of an FPGA. Xilinx offers a service EasyPath whereby
a customized test is developed for a specific customer design that
will run faster and generate a greater yield for the FPGA. This
should reduce production costs by 30% to 80%. Altera's HardCopy is a
migration path from the FPGA to structured ASIC.

Software Tools

Both Xilinx and Altera offer a full suite of software design tools
ranging in price from zero to a few thousand dollars. Large
customers, particularly those involved with ASIC designs, will
likely have purchased and standardized on design flows and tool
sets. They will resist the temptation to change to the inexpensive
tools from the FPGA vendors. However, as more designs migrate to
FPGAs one can speculate on the effect that the availability of cheap
design tools will have on the price of EDA tools.

The ISE tool set from Xilinx comes in four packages: ISE Foundation
at $2,495, Alliance at $1,495, Base X at $695 and WebPack for free.
The ISE Foundation includes advanced timing driven implementation
tools available for programmable logic design, along with design
entry, synthesis and verification capabilities. The less expensive
packages have fewer features and support smaller device sizes.
Additional tools include EDK (Embedded Development Kit) for $495 and
ChipScope Pro for $695. ChipScope Pro embeds logic analyzer cores
into the design. These logic cores allow the user to view all the
internal signals and nodes within an FPGA. EDK supports designs of
processor sub-systems using the IBM PowerPC hard processor core and
the Xilinx's MicroBlaze soft processor core.

The Xilinx ISE Alliance software is for customers who want to
integrate Xilinx programmable logic design software into their
existing EDA tool environment. With ISE Alliance, designers can
choose from a wide range of integrated design solutions, spanning
design capture, synthesis and verification based design
methodologies and tools.

Altera offers Quartus II design software for developing
system-on-a-programmable-chip (SOPC) solutions. The Quartus II
design software offers a unified design flow for the development of
FPGAs, CPLDs, and structured ASICs. Quartus II supports embedded
software programming, synthesis, place-and-route, verification, and
device programming. Altera's Subscription Program includes Quartus
II, ModelSim, MegaCore intellectual property library, Nios embedded
processor evaluation edition and 12 months of software upgrades. The
subscription costs $2,000 for a node-locked PC license. The no-cost
Quartus II Web Edition software includes most of the features
included in the Quartus II software subscription and everything
needed to design for Altera's latest CPLD, low-cost FPGA families
and entry-level members of high-density FPGA families. Other
available tools include SOPC Builder for composing systems defined
at the block or component level and DSP Builder that interfaces with
MATLAB/Simulink tools.

Altera third party alliance program is called the Altera Commitment
to Cooperative Engineering Solutions (ACCESS) Program. Altera and
its EDA partners have collaborate closely to deliver a flexible, yet
seamless design flow for creating system-on-a-programmable-chip
designs. Third party software addresses high-level design, design
entry, synthesis, verification and board level design. The partner
list contains the usual suspects.



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